Nowadays, the constant evolution of the integration capability in CMOS technologies is making possible the development of complex-mixed signal SoC (SoC: System on Chip). This increasing complexity has the associated issue of more complex and hence more expensive test. This issue in view of testing is identified in the SIA roadmap for semiconductors as one of the key problems for present and future mixed-signal SoCs. Regarding the analog parts thereof, usually the test of these parts represents the main bottleneck in this line. Analog circuits are usually tested using functional approaches, often requiring a large data volume processing, high accuracy and high speed ATEs (ATE: Automatic Test Equipment). In addition, these analog parts or analog cores are normally very sensitive to noise and loading effects, which limit the internal monitoring and make their test a difficult task.
Built-in self-test schemes (BIST schemes) have been proved to be a solution to the problems cited above. These BIST schemes consist on a moving part of the required test resources (test stimuli generation, response evaluation, test control circuitry, etc.) from the ATE to the chip including the analog cores. The use of the built-in self-test techniques (BIST techniques) can make a significant difference in terms of test time and costs in comparison to traditional testing with off-chip equipment. The diversity of analog circuit design, the multitude of their performance parameters and their limited observability, make analog and mixed-signal circuit BIST a very challenging problem compared to pure digital circuit BIST. Performing the built-in characterization of all the possible parameters would completely avoid the need of external testing, but the required design time and silicon area overhead would often make that option unaffordable. Nevertheless, a reduction of the testing time, through the built-in aided test of a sub-set of the performance parameters of a mixed-signal IC can positively influence the final costs of the chip.
The on-chip evaluation and generation of periodic signals are of undoubted interest from this point of view. They have wide potential applications in the field of mixed-signal testing as most of these systems (filters, analog-to-digital converters ADCs, digital-to-analog converters DACs, signal conditioners, etc.) can be characterized and tested (frequency domain specification, linearity, etc.) using this kind of stimuli.
Regarding the prior art, reference U.S. Pat. No. 4,740,995 discloses a variable frequency sinusoidal signal generator, in particular for a modem, including a clock generator, a complex digital/analog converter (DAC) based on a R-2R (or C-2C) architecture, and having a frequency variable as a function of a selection signal applied to the generator. The clock generator for outputting a plurality of clock signals having variable frequencies is programmable as a function of a selection signal which constitutes an external signal. Based on reference voltages, and in conjunction with the clock signals utilized as sampling signals a step signal is created having a sinusoidal envelope. The fundamental frequency is a function of the clock signal. The sinusoidal envelope is extracted by a low pass filter section having an adjustable transfer function. The filter section further includes a plurality of capacitors, and switching means is provided for sampling the capacitors at a sampling rate which is a function of the sampling frequency of the digital-to-analog converter. A plurality of capacitors is used for defining particular values of the waveform. The generator can be used in modulators/demodulators or modems for transmitting binary signals on a telephone line.
Moreover, conventional sine wave signal generation methods rely on (i) an analog oscillator consisting of a filtering section and a non-linear feedback mechanism, or (ii) by adapting digital techniques using the scheme and block structure shown in FIG. 12, which facilitates a digital interface for control and programming tasks.
(i) a non-linear feedback mechanism forces the oscillation while the filtering section removes the unwanted harmonics. The quality of the generated signal depends on the linearity and selectivity of the filter (the larger the selectivity is, the larger the purity of the sign signal) and the shape of the non-linear function (smooth functions are needed for low distortion, which requires a lot of area and power. The tuning of the filter allows the programmability of the frequency.
(ii) a direct implementation using memory based synthesizers is not practical because of the area overhead. In conventional systems it is avoided the use of the DAC by exploiting the noise shaping characteristics of EA encoding schemes. They consist of generating a 1-bit stream ΣΔ encoded version of a N-bit digital signal and match the shape of a filter with the noise shaping characteristics of the encoded bit stream.
As is shown in FIG. 12, an external tester A includes a test activation and control device B. The box C refers to the on-chip signal generation, which involves a digital generator D, a D/A-converter E, an analog filter F as well as the specific device under test (DUT) G.
It is valid for single and multitone signals but requires bit-stream lengths and a highly selective filter to remove the noise. In addition, the approach is frequency limited due to the end of the very high over sampling ratios.